`timescale 1ns / 1ps


module porject_1(
    
    input wire a,  // wire 
    input b , // wire 
    
    output wire c_and       ,    
    output wire c_or        ,
    output wire c_not_a     ,
    output wire c_nand      ,
    output wire c_nor       ,
    output wire c_xor       ,
    output reg c_xnor 
    
    );
    
//    and     G_and   (c_and   , a ,b) ;
//    or      G_or    (c_or      , a , b ) ;
//    not     G_not_a      ( c_not_a  , a , b ) ;
//    nand   G_nand       ( c_nand   , a , b ) ;
//    nor    G_nor       ( c_nor    , a , b ) ;
//    xor    G_xor         ( c_xor    , a , b ) ;
//    xnor   G_xnor       ( c_xnor   , a , b ) ;

    assign c_and    = a & b ;       
    assign c_or     = a | b     ;
    assign c_not_a  =  ~a    ;
    assign c_nand   =  ~(a & b)    ;
    assign c_nor    =  ~(a | b)    ;
    assign c_xor    =  a ^ b    ;
    //assign c_xnor   =  (a ^ b)    ;
    
   
   always @* begin
        c_xnor = 1  ;
   
   end
    
    
    
    
endmodule